Silicon Valley Polytechnic Institute

Digital VLSI Design with Verilog

Nanometer ASIC Design Flow

The ASIC development flow at 32, 22, or 14 nanometers has become increasingly complex. Steps that were once decoupled—like logic synthesis and cell placement—now interrelate. Today engineers and managers need to be conversant with all phases in the ASIC flow. RTL designers, for example, need to understand embedded assertions. Software engineers need to know how timing constraints can be violated. Front-end personnel need updating on how silicon chips are fabricated at 32 nm and below. This course fills in the gaps by systematically covering each step, from paper specification to packaged device. Key techniques like logic synthesis, functional verification, formal equivalence checking, design for test, and timing closure are explained using realistic examples that convey valuable insights. Students will perform introductory labs to gain an intuitive feel for using Synopsys synthesis, simulation, and formal tools. The course wraps up with a look at the key technologies for extending Moore's Law such as finFET, etc.


Course Duration

Duration of this course is 12 weeks with classes being held 2 sessions per week. In some cases 2 sessions are combined into one for convenience of students. Training duration per week consists of about 4-6 hours of instructor based training combined by about 6-4 hours of self practice for a total of about 10 hours per week. Tuition Fee for the course includes:

  • 12 weeks of instructor based class room and hands-on training
  • Extensive class notes
  • Certification

Course Schedule & Registration

Please check the SVPTI calendar for schedule or contact CalPT at To register please call CalPT at 408-436-3000 or send request to