Design-for-test technology is rapidly advancing to meet the challenges of detecting faults on nanometer ICs before the devices reach the end user. Testing for delay faults, bridging defects, Iddq, and stuck-open faults is now an essential part of the chip-testing landscape. This hands-on course first covers traditional scan-based techniques in depth. It then builds on that solid foundation by addressing newer techniques that supplement stuck-at testing. Topics also include logic and memory built-in self-test (BIST), and DC and AC JTAG. In lab, students will use Synopsys DFT Compiler to insert test logic, and TetraMAX ATPG to generate test patterns and run fault simulations. Lectures are filled with useful engineering insights. Students will gain real understanding of the underlying technologies behind DFT and ATPG—concepts often glossed over at the workplace in the fast-paced IC industry.
Duration of this course is 12 weeks with classes being held 2 sessions per week. In some cases 2 sessions are combined into one for convenience of students. Training duration per week consists of about 4-6 hours of instructor based training combined by about 6-4 hours of self practice for a total of about 10 hours per week. Tuition Fee for the course includes:
Please check the SVPTI calendar for schedule or contact SVPTI at info@SVPTI.com. To register please call CalPT at 408-436-3000 or send request to info@SVPTI.com.