This hands-on course presents to the students the design of digital integrated circuits using the Verilog digital design language as described in IEEE Standard 1364-2001. By a balanced mixture of lectures and labs, the students are introduced to language constructs in a progressively more complex project environment. During the course, students will become familiar with the use of the Synopsys Design Compiler to synthesize gate-level netlists from behavioral, RTL, and structural Verilog code. The synthesis constraints most useful for area and speed optimization are emphasized. Almost all work is done in the synthesizable subset of the language; logic simulation is treated as an occasional verification method. Other topics include design partitioning, hierarchy decomposition, safe coding styles, assertion-based verification, and design for test.
Duration of this course is 12 weeks with classes being held 2 sessions per week. In some cases 2 sessions are combined into one for convenience of students. Training duration per week consists of about 4-6 hours of instructor based training combined by about 6-4 hours of self practice for a total of about 10 hours per week. Tuition Fee for the course includes:
Please check the CalPT calendar for schedule or contact CalPT at info@CalPT.com. To register please call CalPT or send request to info@CalPT.com.