Silicon Valley Polytechnic Institute


Digital Logic Design Essentials

The course provides a modern introduction to logic design and the basic building blocks used in digital systems. The course starts with a discussion of combinational logic including logic gates, minimization techniques, arithmetic circuits and modern logic devices such as field programmable logic gates. The second part deals with sequential circuits: flip-flops, synthesis of sequential circuits, case studies including counters, registers, random access memories. State machines will be discussed next and illustrated through case studies of more complex systems using programmable logic devices. Different representations including truth table, logic gate, timing diagram, switch representation, state diagram, algorithmic state machine (ASM) chart will be discussed.


Course Duration

Duration of this course is 12 weeks with classes being held 2 sessions per week. In some cases 2 sessions are combined into one for convenience of students. Training duration per week consists of about 4-6 hours of instructor based training combined by about 6-4 hours of self practice for a total of about 10 hours per week. Tuition Fee for the course includes:

  • 12 weeks of instructor based class room and hands-on training
  • Extensive class notes
  • Certification

Course Schedule

Please check the CalPT calendar for schedule or contact CalPT at To register please call CalPT or send request to