This hands-on course prepares the student for digital design and debug at the RTL level. During the course, students will first review key Verilog building blocks. They will then progress to SystemVerilog enhancements, including: structures, arrays, enumerations, and bus interface blocks. In each step-by-step lab, students will synthesize these high-level constructs into nanometer gate logic for ASICs or FPGAs, using Synopsys Design Compiler or Synplify Pro. Coding tips for high speed and low power will be highlighted. Labs will culminate with a self-paced design and debug project. The course includes writing block-level testbenches in SystemVerilog, and embedding assertions directly in the RTL code. As IC chips and IP cores get more complex, exposure to RTL design and debug using SystemVerilog enhancements is becoming more and more of a necessary skill. This course provides a systematic introduction.
Duration of this course is 12 weeks with classes being held 2 sessions per week. In some cases 2 sessions are combined into one for convenience of students. Training duration per week consists of about 4-6 hours of instructor based training combined by about 6-4 hours of self practice for a total of about 10 hours per week. Tuition Fee for the course includes:
Please check the SVPTI calendar for schedule or contact CalPT at info@SVPTI.com. To register please call CalPT at 408-436-3000 or send request to info@SVPTI.com.